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Honored Contributor

14 years ago

ALTDDIO_OUT Clock Timing Constraint Question

I apologize if this is answered elsewhere, but have searched for awhile and have not seen what I think is a definitive answer. I am working on a source-synchronous design in which I am genera...

Altera_Forum

Honored Contributor

14 years ago

Don't do the DDR clock pin. It should work, but painful to do. Instead, have the -source be the physical node of the upstream clock, most likely a PLL output. Look at Case 3 or Case 4 examples in the .zip here, and it will show you:

http://www.alterawiki.com/wiki/source_synchronous_analysis_with_timequest

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ALTDDIO_OUT Clock Timing Constraint Question

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