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Altera_Forum
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14 years ago

ALTDDIO_OUT Clock Timing Constraint Question

I apologize if this is answered elsewhere, but have searched for awhile and have not seen what I think is a definitive answer. I am working on a source-synchronous design in which I am genera...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

What's your set_output_delay constraint look like? That's just the clock setup, which looks correct, although I'm curious what the input is. What device/speed grade? Most stuff should run 150MHz ssync pretty easily.