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Altera_Forum
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14 years ago

ALTDDIO_OUT Clock Timing Constraint Question

I apologize if this is answered elsewhere, but have searched for awhile and have not seen what I think is a definitive answer. I am working on a source-synchronous design in which I am genera...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

The delays will be long, but they should really all cancel out quite a bit. Are you driving ADDR[0] with a 90 degree phase-shifted tap of the PLL?

Also, I am confusing the too, but 150MHz is 300Mbps when DDR, which does get more difficult(150Mbps should be pretty easy).