ALTDDIO_OUT Clock Timing Constraint Question

I had actually read your paper (well, most of it) prior to posting. I didn't think it would work for me, as the data is bidirectional, and I didn't think I would be able to meet my input timings. Very likely though I'm being an idiot, and perhaps I just need to set it up to see how it would work out. I will try it and see what it says.

By the way, I have the SSRAM_CLK assigned to a specific pin - and since I am using an Altera eval board (that has an SSRAM on it) the pin is not assigned to the dedicated PLL output. I also get the following warning, which I think confirms it:

Warning: PLL "PLL_150:PLL_150_inst|altpll:altpll_component|PLL_150_altpll:auto_generated|pll1" output port clk[0] feeds output pin "SSRAM_CLK~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance

So it should be using the global clock tree, so still confused as to why I get so much clock delay at times. :confused:

Thanks again for your time.