ALTDDIO_OUT Clock Timing Constraint Question

The PLL has a dedicated output, whereby its output tap can go directly out a specific port whereby it does not go through the Global clock tree. If you don't have pins assigned, it will generally use this. It's good if you're creating a clock to drive other devices since it has less jitter, but it's terrible for source-synchronous, since the clock going out has no clock tree while the data does, so they're not aligned at all. This dedicated path doesn't have DDR I/O, so once you instantiate them it then goes back to being a regular I/O.

Your setup relationship is 6.666ns. I assume the hold relationship is 0ns. If so, that means the fitter needs to add delay, approximately 3.333ns, to "center the clock". Is that what you want? Please take a look at the link I sent earlier. Basically, I would suggest either:

a) Using two taps of the PLL, one to drive the clock and one for data, and phase-shift the clock one 180 degrees. This will send clock/data in a center-aligned fashion.

b) Use one tap of PLL to drive clock/data. This is to send them edge-aligned. If you want to do this, I change the timing constraints to say the external device will shift the clock into the middle of the data eye.