ALTDDIO_OUT Clock Timing Constraint Question

It is only SDR, so just 150Mbps.

It's odd, I just rebuilt it without using the ALTDDIO (and using the same constraints I showed before), and I fail input setup by nearly 4ns. 2.4ns of that is because of the clock path (why do they become so different?). If I put the ALTDDIOs back in, using the exact same constraints (is that even valid?) I make timing. Looking at the chip planner, it does bounce all over the die. Perhaps I pass with the ALTDDIO because it forces the register near the pin? Do I need to do some floorplanning to get it sane? I haven't had to do that before, so I was hoping to avoid it. :) I've included a screenshot of the failure, for what it is worth.

I was getting very frustrated with it all when I saw the AN433 document, and thought maybe the ALTDDIO would get rid of all my problems!