ALTDDIO_OUT Clock Timing Constraint Question

Thank you for the response. That was the way I originally set it up, but could not figure out how to meet timing. Trying to run at 150MHz now (and eventually 200MHz), and the clock skew + data delay was too much.

For reference, I originally was doing the following without using the ALTDDIO:

create_generated_clock -source {PLL_150_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 5 -multiply_by 6 -duty_cycle 50.00 -name {PLL_150_inst|altpll_component|auto_generated|pll1|clk[0]} {PLL_150_inst|altpll_component|auto_generated|pll1|clk[0]}

create_generated_clock -name {SSRAM_CLK} -source [get_pins {PLL_150_inst|altpll_component|auto_generated|pll1|clk[0]}] -master_clock {PLL_150_inst|altpll_component|auto_generated|pll1|clk[0]} [get_ports {SSRAM_CLK}]

EDIT: I meant to add, after reading AN433, was hoping this would cause the clock and data to launch at near the same time (and if too close, I'd add a phase shift to the outbound clock). Is my reasoning sound?

Thanks again.