--- Quote Start ---
to add an input of 33 bits in an integrator but output 32 bits follow this code:
signal sum : std_logic_vector(32 downto 0) := (others => '0');
process(clk,reset_n)
begin
if reset_n = '0' then
sum <= (others => '0');
elsif clk'event and clk = '1' then
sum <= std_logic_vector(signed(din) + signed(sum));
end if;
end process ;
dout <= sum(31 downto 0);
bit index 31 is assumed dead apparently due to zero insertions so becomes sign bit.
--- Quote End ---
Now it is working well now this output of 32 bits will be the input to the next stage and the output for the next integrator will be 34 bits so can you tell me how to add a 32 bit input and the 34 bit feedback signal as shown in the attached file that i have sent it to you.
If it is possible with the resize function can you write the vhdl code for the two stages of integrator section.I have written the code as below
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity integrator is
port(
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(32 downto 0)
--dout:out std_logic_vector(32 downto 0)
);
end integrator;
architecture Behavioral of integrator is
--signal ifilterout30:std_logic_vector(31 downto 0):=(others =>'0');
signal ifilterout31:std_logic_vector(32 downto 0):=(others =>'0');
signal ifilterout32:std_logic_vector(31 downto 0):=(others =>'0');
signal ifilterout34:std_logic_vector(33 downto 0):=(others =>'0');
signal ifilterout33:std_logic_vector(33 downto 0):=(others =>'0');
begin
process(Clk,reset)
begin
if reset='0' then
ifilterout31<="000000000000000000000000000000000";
ifilterout33<="0000000000000000000000000000000000";
-- dout<="000000000000000000000000";
elsif clk'event and clk='1' then
-- ifilterout30 <= std_logic_vector(resize(signed(din),32));
ifilterout31 <= std_logic_vector(signed(din)+signed(ifilterout31));
ifilterout32 <=ifilterout31(31 downto 0);
ifilterout34 <= std_logic_vector(resize(signed(ifilterout32),34));
ifilterout33 <= std_logic_vector(signed(ifilterout34)+signed(ifilterout33));
-- ifilterout33 <= std_logic_vector(resize(signed( ifilterout32),34));
-- ifilterout32 <= std_logic_vector(resize(signed(ifilterout31),34));
-- dout <= ifilterout31;
-- ifilterout32 <= ifilterout31;
-- ifilterout32 <= ifilterout31;
end if;
end process ;
end Behavioral;
please tell what changes to make in the above code so that the output comes.The output is coming as "xxxx.....x" throughout the second integrator stage but as you have told there is no problem in the first integrator stage.
Honored Contributor
