Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

about vhdl code for cic interpolation filter

i am attaching one pdf file based on cic filter.In the bitgrowth section the author has mentioned about the increase in the bits at the output stage .Suppose if i am writing a vhdl code for cic inter...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

--- Quote Start ---

you need sign extend:

data_24 <= std_logic_vector(resize(signed(data_23)),24) + resize(signed(data_23b)),24);

--- Quote End ---

i have tried the above code .Why you are mentioning signed and then std_logic_vector for performing addition.Is data_24 a signed number or unsigned number or you have mentioned it with std_logic_vector?.can you show it with an example in vhdl code?