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my bracket syntax error
data_24 <= std_logic_vector(resize(signed(data_23),24) + resize(signed(data_23b),24));
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According to the equation given in the cic paper introduction which i have attached previously if for M=1 the output of the first integrator section should be one bit less than the input to the first integrator .As per as my factors of N,M, R that is N=9,M=1,R=8 you got as you have seen so the output of first integrator stage is 32 bits.Now if i have to use the resize function in the integrator stage .I am attaching an integrator circuit and also i am posting my vhdl code that i have written for the integrator stage.Can you tell me the problem in my vhdl code.The input is 33 bit but the output should be 32 bit as per the calculation that you have done in matlab.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity integrator is
port(
clk:in std_logic;
reset:in std_logic;
din:in std_logic_vector(32 downto 0);
dout:out std_logic_vector(32 downto 0)
);
end integrator;
architecture Behavioral of integrator is
signal ifilterout31:std_logic_vector(32 downto 0):=(others =>'0');
begin
process(Clk,reset)
begin
if reset='0' then
ifilterout31<="00000000000000000000000000000000";
-- ifilterout32<="000000000000000000000000";
-- dout<="000000000000000000000000";
elsif clk'event and clk='1' then
ifilterout31 <= std_logic_vector(resize((signed(din)+signed(ifilte rout31)),31));
-- dout <= ifilterout31;
-- ifilterout32 <= ifilterout31;
-- ifilterout32 <= ifilterout31;
end if;
end process ;
end Behavioral;
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