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Altera_Forum
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13 years ago

about vhdl code for cic interpolation filter

i am attaching one pdf file based on cic filter.In the bitgrowth section the author has mentioned about the increase in the bits at the output stage .Suppose if i am writing a vhdl code for cic inter...
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Altera_Forum
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12 years ago

to add up 32 bits input in an integrator that outputs 34 bits here we go: 


signal sum : std_logic_vector(33 downto 0) := (others => '0');
process(reset_n,clk)
if reset_n = '0' then
   sum <= (others => '0');
elsif rising_edge(clk) then
   sum <= std_logic_vector(signed(sum) + resize(signed(din),34));
end if;
end process;
dout <= sum;