about vhdl code for cic interpolation filter

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i have tried the above code .Why you are mentioning signed and then std_logic_vector for performing addition.Is data_24 a signed number or unsigned number or you have mentioned it with std_logic_vector?.can you show it with an example in vhdl code?

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if your signals are signed you can ignore std_logic_vector and signed expression.

I have assumed your signals are all std_logic_vector and internal computation is signed.

data_24 <= resize(data23,24) + resize(data23b,24);