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Altera_Forum
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13 years ago

about vhdl code for cic interpolation filter

i am attaching one pdf file based on cic filter.In the bitgrowth section the author has mentioned about the increase in the bits at the output stage .Suppose if i am writing a vhdl code for cic inter...
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Altera_Forum
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12 years ago

to add an input of 33 bits in an integrator but output 32 bits follow this code: 


signal sum : std_logic_vector(32 downto 0) := (others => '0');
process(clk,reset_n)
begin 
  if reset_n = '0' then 
    sum  <= (others => '0');
  elsif clk'event and clk = '1' then
    sum  <= std_logic_vector(signed(din) + signed(sum));
end if;       
end process ;  
dout <= sum(31 downto 0);

bit index 31 is assumed dead apparently due to zero insertions so becomes sign bit.