--- Quote Start ---
you need sign extend:
data_24 <= std_logic_vector(resize(signed(data_23)),24) + resize(signed(data_23b)),24);
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actually i have tried a simple code as you have mentioned above as below
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.numeric_std.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity project1 is
port(a:in STD_LOGIC_vector(23 downto 0);
b:in STD_LOGIC_vector(23 downto 0);
z:out STD_LOGIC_vector(24 downto 0));
end project1;
architecture Behavioral of project1 is
begin
z<=STD_LOGIC_vector (resize(signed(a)),24)+resize(signed(b)),24);
end Behavioral;
and the error i have got is
ERROR:HDLParsers:3324 - "D:/projects final/signextension/project1.vhd" Line 42. IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value.
ERROR:HDLParsers:3324 - "D:/projects final/signextension/project1.vhd" Line 42. IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value.
ERROR:HDLParsers:854 - "D:/projects final/signextension/project1.vhd" Line 42. The expression can not be converted to type STD_LOGIC_vector.
ERROR:HDLParsers:3324 - "D:/projects final/signextension/project1.vhd" Line 42. IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value.
ERROR:HDLParsers:3324 - "D:/projects final/signextension/project1.vhd" Line 42. IN mode Formal NEW_SIZE of resize with no default value must be associated with an actual value.
ERROR:HDLParsers:164 - "D:/projects final/signextension/project1.vhd" Line 42. parse error, unexpected CLOSEPAR, expecting SEMICOLON
Process "Check Syntax" failed
What is the problem with my code can you suggest me?
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