i am attaching one pdf file based on cic filter.In the bitgrowth section the author has mentioned about the increase in the bits at the output stage .Suppose if i am writing a vhdl code for cic interpolation stage for example let differential delay M=1, Interpolation factor R=8,Input bit size be 23 and number of comb sections and integrator sections be N=9.Then how the output bit size change for each comb section.Can anybody explain me with the above mentioned parameters?

according to given equation :for decimator, last comb output bits = 9 * log2(8*1) + 23 = 50 bits and it says, the same should be used at each comb or integrator stage. Leave truncation to final output. for interpolator: last stage = 23 + 9 -1 = 31 bits and stage before last requires 23+8-1 = 30 bits and so on

--- Quote Start --- according to given equation :for decimator, last comb output bits = 9 * log2(8*1) + 23 = 50 bits and it says, the same should be used at each comb or integrator stage. Leave truncation to final output. for interpolator: last stage = 23 + 9 -1 = 31 bits and stage before last requires 23+8-1 = 30 bits and so on --- Quote End --- whether this increase in bits should be applied at each stage of comb and integrator section or only at end of each stage of comb section or only at end of each stage of integrator section

For interpolating CIC I assume (from the wording of the document) that it applies to each stage(be it comb or integrator). You try it and tell us.

--- Quote Start --- For interpolating CIC I assume (from the wording of the document) that it applies to each stage(be it comb or integrator). You try it and tell us. --- Quote End --- After further work it turned out that my last statement needs correction. The best thing is run this matlab program and read (d): Bin = 23; %input width N = 9; %stages of comb or integrator M = 1; %differential delay R = 8; %interpolation rate %cic decimator at any stage Bout = N * log2(R*M) + Bin; %cic interpolator per ith stage %stages 1~N for i = 1:N G = 2^i; Bout = Bin + log2(G); d(i) = Bout; end %N+1 ~ 2N stages for i = N+1:N*2 G = (2^(2*N-1)*(R*M)^(i-N))/R; Bout = Bin + log2(G); d(i) = Bout; end for i = 1:N*2 fprintf('%i %i\r',i,d(i)); end

--- Quote Start --- After further work it turned out that my last statement needs correction. The best thing is run this matlab program and read (d): Bin = 23; %input width N = 9; %stages of comb or integrator M = 1; %differential delay R = 8; %interpolation rate %cic decimator at any stage Bout = N * log2(R*M) + Bin; %cic interpolator per ith stage %stages 1~N for i = 1:N G = 2^i; Bout = Bin + log2(G); d(i) = Bout; end %N+1 ~ 2N stages for i = N+1:N*2 G = (2^(2*N-1)*(R*M)^(i-N))/R; Bout = Bin + log2(G); d(i) = Bout; end for i = 1:N*2 fprintf('%i %i\r',i,d(i)); end --- Quote End --- after checking the matlab code above the value of d is as below 1 24 2 25 3 26 4 27 5 28 6 29 7 30 8 31 9 32 10 40 11 43 12 46 13 49 14 52 15 55 16 58 17 61 18 64 Now my question is with 23 bit input data how to write vhdl code so that the ouput data width is 24 and follows.Since addition of 2 23 bit input data as shown in the comb section of the cic interpolation is 23 bit data and if i specify output data widthto be 24 there will be syntax error while synthesizing the vhdl code that datatypes are not matching.Can you give solution for this problem?

about vhdl code for cic interpolation filter

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Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
The final output ifilterout33 is coming as undefined . I tried as you said.But still there is problem in the output.
--- Quote End ---

I guess you are talking about functional simulation resuts? The uninitialized register ifilterout32 is propagating to the last integrator stage.

You need to initialize all register variables in functional simulation.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
I guess you are talking about functional simulation resuts? The uninitialized register ifilterout32 is propagating to the last integrator stage.

You need to initialize all register variables in functional simulation.
--- Quote End ---

Is the initialization that i have done in the given code is not enough?
Altera_Forum
Honored Contributor
12 years ago
You are right, I didn't look thoroughly at the code. In this case, I expect that "undefined" is propagating from din. You'll need to look at the exact waveforms for each register to identify where undefines comes from, ore use a respective trace function in Modelsim.

I also noticed that it's apparently a Xilinx project. This is not the right forum to get help for possible problems with Xilinx tools.

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about vhdl code for cic interpolation filter

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