Forum Discussion

Icon for Honored Contributor rank

Honored Contributor

14 years ago

Worst slack values are Negative for Removal

HI ,

I am trying to run the NIOSII example of led from the nios2 hardware manual.I could generate the nios 2 system.And also integrate it with the Quartus.But when I compile the system in quartus I get the Worst-case Slack values are negative numbers for Removal in Time quest timing Analyser.

But the document says that :

The Worst-case Slack values are positive numbers for Setup, Hold, Recovery and Removal. If any of these values are negative, the design might not operate properly in hardware. To meet timing, adjust Quartus II assignments to optimize fitting, or reduce the oscillator frequency driving the FPGA.

I cant reduce the clock frequency as I using the min freq of 50 Mhz.

How to optimise the fitting? I tried to find it but couldnt get it.

Can some one explain what the worst slack values for removal means?

I also have these critical warnings:

Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)

Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)

Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold)

Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)

Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)

Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold)

Critical Warning: Timing requirements not met

Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)

Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)

Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold)

Critical Warning: Timing requirements not met

Critical Warning: The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.

Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Rise) (setup and hold)

Critical Warning: From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning: From altera_reserved_tck (Fall) to altera_reserved_tck (Fall) (setup and hold)

Critical Warning: From sopc_clk (Rise) to sopc_clk (Rise) (setup and hold)

Critical Warning: From sopc_clk (Fall) to sopc_clk (Rise) (setup and hold)

Critical Warning: From sopc_clk (Rise) to sopc_clk (Fall) (setup and hold)

Critical Warning: Timing requirements not met

:confused:

Regards

Sneha

17 Replies

Altera_Forum
Honored Contributor
14 years ago
Well, you can always reduce the frequency by adding a pll in the clock path.
It might be that just adding a pll already fixes your problem, but if timing already fails at 50MHz, something in your design seems really off.

I usually define every altera_reserved_* as false path, but that might not help you just yet.
Altera_Forum
Honored Contributor
14 years ago
HI ,

I reduced the clk frequency to 25 Mhz.But still I have the same problem.
Earlier I had negative values only in altera reserved clk (worst case slack) and altera reserved clk (Design wide TNS) .

But now at 25 Mhz I get negative values even in sopc clk.

How are these negative values goin to affect the H/W.
Can you explain?
Its my first demo with Altera and I dont understand it.
Altera_Forum
Honored Contributor
14 years ago
With a .sdc file open, go to the Quartus II --> edit --> insert template. If you look under timequest you should find the JTAG constraints. Those are the ones you are missing and these are the types of failures you can't fix by changing the clock frequency since recovery/removal paths have to do with the reset path and not the data path. For board delays I just eyeball it and overestimate....... although I probably just use 1us for the JTAG logic and call it a day most of the time :)
Altera_Forum
Honored Contributor
14 years ago
Hi,

This is the .sdc file I received with the demo.
# Update -period with clock period (in nanoseconds) of the clock driving the fpga
create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT]
# Setting LED outputs as false path, since no timing requirement
set_false_path -from * -to [get_ports LEDG
[*]]
# Constraining JTAG interface# TCK port
create_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]# cut all paths to and from tck
set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]# constrain the TDI port
set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]# constrain the TMS port
set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]# constrain the TDO port# JTAG Signal Constraints constrain the TCK port
create_clock -name tck -period __period [get_ports altera_reserved_tck]# Cut all paths to and from tck
set_clock_groups -asynchronous -group [get_clocks tck]# Constrain the TDI port
set_input_delay -clock tck -clock_fall __tdiBoardDelayValue [get_ports altera_reserved_tdi]# Constrain the TMS port
set_input_delay -clock tck -clock_fall __tmsBoardDelayValue [get_ports altera_reserved_tms]# Constrain the TDO port
set_output_delay -clock tck -clock_fall __tdoBoardDelayValue [get_ports altera_reserved_tdo]

set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo]

I followed the said proceedure advised by you.

And I inserted a user template with the jtag constrains as
# JTAG Signal Constraints constrain the TCK port
create_clock -name tck -period __period 1000[get_ports altera_reserved_tck]# Cut all paths to and from tck
set_clock_groups -asynchronous -group 1000[get_clocks tck]# Constrain the TDI port
set_input_delay -clock tck -clock_fall __tdiBoardDelayValue 1000[get_ports altera_reserved_tdi]# Constrain the TMS port
set_input_delay -clock tck -clock_fall __tmsBoardDelayValue 1000[get_ports altera_reserved_tms]# Constrain the TDO port
set_output_delay -clock tck -clock_fall __tdoBoardDelayValue 1000[get_ports altera_reserved_tdo]

Here I set all the timing constraint parameters with jtag in the sdc file.

But still the worst slack value is negative:

altera_reserved_tck 11.428 0.161 43.369 -2.246 29.289 Worst-case Slack 5.911 0.112 3.557 -2.246 9.546

altera_reserved_tck 0.000 0.000 0.000 -2.246 0.000
Design-wide TNS 0 .0 0.0 0.0 -2.246 0.0

There is problem in the fitter design
I am using cyclone 3 development board with EP3C120F780C7

I am newbie with altera
Please help?

Icon for Honored Contributor rank

Honored Contributor

Use something like this instead:

# JTAG Signal Constraints constrain the TCK port (uncomment the line below if altera_reserved_tck isn't already defined)# create_clock -name tck -period 100 #  Cut all paths to and from tck
set_clock_groups -asynchronous -group #  Constrain the TDI port
set_input_delay -clock altera_reserved_tck -clock_fall 1 #  Constrain the TMS port
set_input_delay -clock altera_reserved_tck -clock_fall 1 #  Constrain the TDO port
set_output_delay -clock altera_reserved_tck -clock_fall 1

Altera_Forum
Honored Contributor
14 years ago
HI ,

I modified the constraint file with this :
# Update -period with clock period (in nanoseconds) of the clock driving the fpga
create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT]
# Setting LED outputs as false path, since no timing requirement
set_false_path -from * -to [get_ports LEDG
[*]]

# Constraining JTAG interface# TCK port
create_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]# cut all paths to and from tck
set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]# constrain the TDI port
set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]# constrain the TMS port
set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]# constrain the TDO port
set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo]
# JTAG Signal Constraints constrain the TCK port
create_clock -name tck -period 100 [get_ports altera_reserved_tck]# Cut all paths to and from tck
set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port
set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]# Constrain the TMS port
set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]# Constrain the TDO port
set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo]

but still the worst slack time for removal is negative.

altera_reserved_tck 0.000 0.000 0.000 -2.347 0.000
Design-wide TNS 0.0 0.0 0.0 -2.347 0.0

altera_reserved_tck 43.109 0.181 42.831 -2.347 29.289 Worst-case Slack 6.011 0.082 3.704 -2.347 9.550

But it says that:
# Update -period with clock period (in nanoseconds) of the clock driving the fpga

Should nt we put the value in nanosec?
Altera_Forum
Honored Contributor
14 years ago
Instead of create_clock you could use
"derive_pll_clocks -create_base_clocks"
With this Timequest should read the values from the PLL and SOPC.
Altera_Forum
Honored Contributor
14 years ago
Hi,

But I am not using the pll.
I was able to download the program in the board and run it with the negative slack removal values itself.

What are these values important for ?Can anyone explain?
Altera_Forum
Honored Contributor
14 years ago
Timequest estimates timing values for corner cases (at least it should if configured correctly).
So if your timing fails, it will fail at -40°C or at 100°C (or whatever corner case is defined). It will probably work on your desk, but when deployed to the field it might fail occasionally, or regularly, depending on the amount of bad luck you have.
Altera_Forum
Honored Contributor
14 years ago
Hey thnks mcr42..

But can you explain what in specific is worst case slack for recovery and removal.The one which I am getting as negative in this design are

Worst case slack for: altera reserved tck : removal

Design wide TNS :altera reserved tck :removal

What are the removal and the recovery timings for ?I am aware with the setup and the hold timings.

Thanks!!!