Forum Discussion
Altera_Forum
Honored Contributor
15 years agoWith a .sdc file open, go to the Quartus II --> edit --> insert template. If you look under timequest you should find the JTAG constraints. Those are the ones you are missing and these are the types of failures you can't fix by changing the clock frequency since recovery/removal paths have to do with the reset path and not the data path. For board delays I just eyeball it and overestimate....... although I probably just use 1us for the JTAG logic and call it a day most of the time :)