Honored Contributor
Honored ContributorHi,
This is the .sdc file I received with the demo. # Update -period with clock period (in nanoseconds) of the clock driving the fpga create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT] # Setting LED outputs as false path, since no timing requirement set_false_path -from * -to [get_ports LEDG [*]] # Constraining JTAG interface# TCK port create_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]# cut all paths to and from tck set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]# constrain the TDI port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]# constrain the TMS port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]# constrain the TDO port# JTAG Signal Constraints constrain the TCK port create_clock -name tck -period __period [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group [get_clocks tck]# Constrain the TDI port set_input_delay -clock tck -clock_fall __tdiBoardDelayValue [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock tck -clock_fall __tmsBoardDelayValue [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock tck -clock_fall __tdoBoardDelayValue [get_ports altera_reserved_tdo] set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo] I followed the said proceedure advised by you. And I inserted a user template with the jtag constrains as # JTAG Signal Constraints constrain the TCK port create_clock -name tck -period __period 1000[get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group 1000[get_clocks tck]# Constrain the TDI port set_input_delay -clock tck -clock_fall __tdiBoardDelayValue 1000[get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock tck -clock_fall __tmsBoardDelayValue 1000[get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock tck -clock_fall __tdoBoardDelayValue 1000[get_ports altera_reserved_tdo] Here I set all the timing constraint parameters with jtag in the sdc file. But still the worst slack value is negative: altera_reserved_tck 11.428 0.161 43.369 -2.246 29.289 Worst-case Slack 5.911 0.112 3.557 -2.246 9.546 altera_reserved_tck 0.000 0.000 0.000 -2.246 0.000 Design-wide TNS 0 .0 0.0 0.0 -2.246 0.0 There is problem in the fitter design I am using cyclone 3 development board with EP3C120F780C7 I am newbie with altera Please help?
