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Altera_Forum
Honored Contributor
15 years agoHI ,
I modified the constraint file with this : # Update -period with clock period (in nanoseconds) of the clock driving the fpga create_clock -name sopc_clk -period 20 [get_ports PLD_CLOCKINPUT] # Setting LED outputs as false path, since no timing requirement set_false_path -from * -to [get_ports LEDG [*]] # Constraining JTAG interface# TCK port create_clock -name altera_reserved_tck -period 100 [get_ports altera_reserved_tck]# cut all paths to and from tck set_clock_groups -exclusive -group [get_clocks altera_reserved_tck]# constrain the TDI port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdi]# constrain the TMS port set_input_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tms]# constrain the TDO port set_output_delay -clock altera_reserved_tck 20 [get_ports altera_reserved_tdo] # JTAG Signal Constraints constrain the TCK port create_clock -name tck -period 100 [get_ports altera_reserved_tck]# Cut all paths to and from tck set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]# Constrain the TDI port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdi]# Constrain the TMS port set_input_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tms]# Constrain the TDO port set_output_delay -clock altera_reserved_tck -clock_fall 1 [get_ports altera_reserved_tdo] but still the worst slack time for removal is negative. altera_reserved_tck 0.000 0.000 0.000 -2.347 0.000 Design-wide TNS 0.0 0.0 0.0 -2.347 0.0 altera_reserved_tck 43.109 0.181 42.831 -2.347 29.289 Worst-case Slack 6.011 0.082 3.704 -2.347 9.550 But it says that: # Update -period with clock period (in nanoseconds) of the clock driving the fpga Should nt we put the value in nanosec?