Nios II won't work after uploaded to the board

check that you provide a valid clock to your CPU and that you meet timing requirements.

Check also the polarity of the reset signal. IIRC the reset input on a SOPC component is active low (which is indicated by a "_n" at the end of the signal name) and I don't remember what is the polarity of a push button input on that kit.

The .sof generated is not time limited, I use a license file properly configured.

I provide a 100Mhz clock to the processor. I pick the native DE2 50 Mhz clock (PIN_N2) and pass through a PLL to double the frequency. The clock to the SDRAM chip is 50Mhz phase shifted -54 degrees by the same PLL. I would post a screenshot, but Altera forum wouldn't let me.

Regarding the RESET signal, I changed from a push button to a switch, with no success on both positions of the switch.

I know the problem isn't the chip because I can use other precompiled nios2 with success.

I will try other clock setups and see what happens.

Also, I have one doubt that's bugging me. After I generated the processor and put on the .bdf file, I created all of the input/output/bidir portsby hand (I know now that this can be done automatically). But when I open the Assignments Editor, only the pins of the nios2 block appear, and none of the ports. Is this normal? I had to manually enter the names of the ports.

Thanks

Indeed, it was the clock. When I configure it with 100MHz, through the PLL, the errors I described show up. However, when directly connected to the 50Mhz native clock, it works.

I am able to upload an image to the sdram chip, but it fails to verify the uploaded file.

Did you declare your clock in an sdc file for timequest and did you constrain your inputs/outputs? 100MHz should be reachable.

I don't have any experience on that board with the sdram so I can't help you there, but it could be easier to start with a design example that works and modify it to suit your needs instead of starting from scratch.

I'm not at sure why the SDRAM clock has to be 'early' - since the simple timing analysis then gives errors. The errors can be removed by changing the skew (I increased it a bit - more -ve) - but then the sdram didn't work!

IIRC the cyclone dev board needed about -3.4ns, I suspect this is actually independant of the clock speed!

Daixiwen,

This is really puzzling me. I'm not experienced in VHDL or Verilog. I've built the system in a Block Diagram File, following instructions from the book cited. It is really simple. It has a nios2 block and a PLL block. To each of them I wired several input/output/bidir ports. Then I assigned the pins in the Assignment Editor.

When I configure the PLL with one 50Mhz, -3ns output (to the SDRAM) and wire the native 50MHz clock directly to the clk of the Nios II, I'm able to configure the FPGA, upload a File to the SDRAM but not run the file (it doesn't VERIFY the sdram)

When I configure the PLL with two outputs, one of them 50 MHz -3ns (to the SDRAM) and the other 100MHz without delay (to the clk of nios2), the processor freezes (it PAUSES, and cannot be unpaused).

So I strongly suspect that I'm not using the PLL well. Or I am doing something really really dumb and not seeing it. I'm trying everything that I find, but with no success.

About your questions: I do not declare the clock anywhere, and don't know how to constrain inputs/outputs. If you give me some pointers on that I would really appreciate. The only reference designs that I have (for the DE2-35 board) are the ones provided by the book. But they do not use MMU, and use really old components (7.1) for Nios. I have several others references, but they're both not for DE2 and not a BDF file. Would be better if I make the system in verilog, instead of a Block Diagram File?

dsl,

I tried -3ns and -4ns for the SDRAM, I will try 3.4ns and other close values.

Thank you people for the help.

There are some screenshots that I took:

Block Diagram File, showing the PLL:

http://img696.imageshack.us/img696/519/nios.th.png (http://img696.imageshack.us/i/nios.png/)

Configs I tried:

1. c0: 50Mhz -3ns [SDRAM] (cpu directly connected to system clock)

2. c0 :50Mhz -3ns [SDRAM] c1: 100Mhz 0ns [CPU]

3. c0: 100Mhz -3ns [SDRAM] c2: 100Mhz 0ns [CPU]

I tried even to create the PLL inside the SOPC, same results.

SOPC configuration:

http://img130.imageshack.us/img130/4353/sopc.th.png (http://img130.imageshack.us/i/sopc.png/)

The adresses are all below 0x0100 0000 for the components, except for sdram, which is at 0x1000 0000.

When I modified the clock fed by the PLL, I accordingly changed the clk.

CPU config:

http://img207.imageshack.us/img207/8817/sopc2.th.png (http://img207.imageshack.us/i/sopc2.png/)

I've tried different values for reset and exception vector, including the ofsset 5000000 cited here in some thread.

If you need more screenshots, or the entire project, I will promptly upload.

Thanks in advance

Maybe a dumb question, but since you thought you might be doing something wrong with the PLL.

Are you aware of the fact that the PLL (at least the one created by the MegaWizzard) uses an active HIGH reset?

edit: just noticed in the files you uploaded that you don't have a reset for your pll, maybe that's an idea too.

For the 50 MHz clock coming from the board you will have to add a line like this to an .sdc timing file:

create_clock -name {CLOCK50MHz} -period 5.000 [get_ports { CLK50MHz }]

and

derive_clock_uncertainty

Somewhere in an .sdc file you will also need to constrain the PLL clocks.

derive_pll_clocks

I don't know if the SOPC builder generates a .sdc file for the SDRAM for you (I know for the DDR controllers it does).

I would also recommended running the software from on-chip memory first. And testing the SDRAM like that.