Nios II won't work after uploaded to the board

Daixiwen,

This is really puzzling me. I'm not experienced in VHDL or Verilog. I've built the system in a Block Diagram File, following instructions from the book cited. It is really simple. It has a nios2 block and a PLL block. To each of them I wired several input/output/bidir ports. Then I assigned the pins in the Assignment Editor.

When I configure the PLL with one 50Mhz, -3ns output (to the SDRAM) and wire the native 50MHz clock directly to the clk of the Nios II, I'm able to configure the FPGA, upload a File to the SDRAM but not run the file (it doesn't VERIFY the sdram)

When I configure the PLL with two outputs, one of them 50 MHz -3ns (to the SDRAM) and the other 100MHz without delay (to the clk of nios2), the processor freezes (it PAUSES, and cannot be unpaused).

So I strongly suspect that I'm not using the PLL well. Or I am doing something really really dumb and not seeing it. I'm trying everything that I find, but with no success.

About your questions: I do not declare the clock anywhere, and don't know how to constrain inputs/outputs. If you give me some pointers on that I would really appreciate. The only reference designs that I have (for the DE2-35 board) are the ones provided by the book. But they do not use MMU, and use really old components (7.1) for Nios. I have several others references, but they're both not for DE2 and not a BDF file. Would be better if I make the system in verilog, instead of a Block Diagram File?

dsl,

I tried -3ns and -4ns for the SDRAM, I will try 3.4ns and other close values.

Thank you people for the help.