Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThere are some screenshots that I took:
Block Diagram File, showing the PLL: http://img696.imageshack.us/img696/519/nios.th.png (http://img696.imageshack.us/i/nios.png/) Configs I tried: 1. c0: 50Mhz -3ns [SDRAM] (cpu directly connected to system clock) 2. c0 :50Mhz -3ns [SDRAM] c1: 100Mhz 0ns [CPU] 3. c0: 100Mhz -3ns [SDRAM] c2: 100Mhz 0ns [CPU] I tried even to create the PLL inside the SOPC, same results. SOPC configuration: http://img130.imageshack.us/img130/4353/sopc.th.png (http://img130.imageshack.us/i/sopc.png/) The adresses are all below 0x0100 0000 for the components, except for sdram, which is at 0x1000 0000. When I modified the clock fed by the PLL, I accordingly changed the clk. CPU config: http://img207.imageshack.us/img207/8817/sopc2.th.png (http://img207.imageshack.us/i/sopc2.png/) I've tried different values for reset and exception vector, including the ofsset 5000000 cited here in some thread. If you need more screenshots, or the entire project, I will promptly upload. Thanks in advance