Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThe .sof generated is not time limited, I use a license file properly configured.
I provide a 100Mhz clock to the processor. I pick the native DE2 50 Mhz clock (PIN_N2) and pass through a PLL to double the frequency. The clock to the SDRAM chip is 50Mhz phase shifted -54 degrees by the same PLL. I would post a screenshot, but Altera forum wouldn't let me. Regarding the RESET signal, I changed from a push button to a switch, with no success on both positions of the switch. I know the problem isn't the chip because I can use other precompiled nios2 with success. I will try other clock setups and see what happens. Also, I have one doubt that's bugging me. After I generated the processor and put on the .bdf file, I created all of the input/output/bidir portsby hand (I know now that this can be done automatically). But when I open the Assignments Editor, only the pins of the nios2 block appear, and none of the ports. Is this normal? I had to manually enter the names of the ports. Thanks