Nios II won't work after uploaded to the board

Maybe a dumb question, but since you thought you might be doing something wrong with the PLL.

Are you aware of the fact that the PLL (at least the one created by the MegaWizzard) uses an active HIGH reset?

edit: just noticed in the files you uploaded that you don't have a reset for your pll, maybe that's an idea too.

For the 50 MHz clock coming from the board you will have to add a line like this to an .sdc timing file:

create_clock -name {CLOCK50MHz} -period 5.000 [get_ports { CLK50MHz }]

and

derive_clock_uncertainty

Somewhere in an .sdc file you will also need to constrain the PLL clocks.

derive_pll_clocks

I don't know if the SOPC builder generates a .sdc file for the SDRAM for you (I know for the DDR controllers it does).

I would also recommended running the software from on-chip memory first. And testing the SDRAM like that.