Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI'm not at sure why the SDRAM clock has to be 'early' - since the simple timing analysis then gives errors. The errors can be removed by changing the skew (I increased it a bit - more -ve) - but then the sdram didn't work!
IIRC the cyclone dev board needed about -3.4ns, I suspect this is actually independant of the clock speed!