Forum Discussion
Honored Contributorethernet auto-negotiation blocked?
Hi, I'm building a data acquisition and transfer system using Ethernet. The data source is continuous and has a throughput of 160 Mbps. Since the onboard Ethernet only supports 10/100 Base-T, I'm considering to use onboard SDRAM to store a block of data and then transfer to PC over Ethernet. I use DMA to write data in SDRAM and then use UDP to transfer data. The heap and stack are located in SDRAM, so the offset of SDRAM for data register will cause some exceptions. The onboard SDRAM has the size of 32M*8-bit. For example, （1） when I write SDRAM at 0x00001000 away from the base address of SDRAM, only 16kB data can be written into SDRAM； （2） when I write SDRAM　ａｔ　0x00004000 away from the base address of SDRAM, the system will be blocked at Ethernet auto-negotiation; (3) when I write SDRAM at 0x00010000, then 1MB data can be written into SDRAM. Sometimes, it will give me the error information like Ethernet exit. I don't know the reason to cause such phenomenon. Any ideas or suggestion are welcome! Thank you in advance!
Eunice12 Replies
Altera_ForumWhere are you running your code from? Not the SDRAM that you're writing to, I hope... Unless you're quite careful, you're going to be overwriting code/data from your tcp/ip program.
- slacker- Altera_Forum--- Quote Start --- Where are you running your code from? Not the SDRAM that you're writing to, I hope... Unless you're quite careful, you're going to be overwriting code/data from your tcp/ip program. - slacker --- Quote End --- I think my program code is running on onboard sram, rather than sdram. The configuration is as following: .txt ext_sram .rodata onchip_64kbram .wrdata onchip_64kbram .heap sdram .stack sdram
- Altera_Forum
Ok....where are your processor's Exception and Reset addresses? If either is pointed at the SDRAM, then that could be the source of the behavior you're seeing
- Altera_Forum--- Quote Start --- Ok....where are your processor's Exception and Reset addresses? If either is pointed at the SDRAM, then that could be the source of the behavior you're seeing --- Quote End --- Hi, I have no idea about this issue. Since in my system library, the option "Use a separate exception stack" is grayed and disabled. So there is no value shown for "Exception stack memory" and "Maximum exception stack size". Does this mean my processor's exception is located in SDRAM? I am really confused about this. Thanks!
- Altera_Forum
You have to look at your hardware configuration...specifically, the Nios II's settings...in SOPC Builder in order to find where your Reset/Exception addresses are located.
- Altera_Forum
Thank you very much. I find the information about reset and exception address. The processor's reset vector is located in ext_flash with offset 0x0 and exception vector is located in sdram with offset 0x20. I think it might be the reason. Thank you again.
BTW, I would like to know whether there is any requirement about these two vectors' location. - Altera_Forum
The Reset address should be pointed at some non-volatile location (onchip memory or flash). The Exception address should be pointed at RAM....in your case either onchip or SRAM, _not_ SDRAM :-)
Cheers, - slacker - Altera_Forum
if you use malloc() calls to allocate a bloc of memory and use it to get the data from the DMA, you won't have any conflicts, even with other stuff put in sdram.
- Altera_Forum--- Quote Start --- The Reset address should be pointed at some non-volatile location (onchip memory or flash). The Exception address should be pointed at RAM....in your case either onchip or SRAM, _not_ SDRAM :-) Cheers, - slacker --- Quote End --- Thank you very much, slacker. However, the problem still exists when I arrange the reset vector in flash and exception vector in sram.
- Altera_Forum--- Quote Start --- if you use malloc() calls to allocate a bloc of memory and use it to get the data from the DMA, you won't have any conflicts, even with other stuff put in sdram. --- Quote End --- Hi, I don't think malloc() function can allocate a block of memory in SDRAM. In my understanding, it will just allocate the memory of onchip-ram. Is that right?
