Forum Discussion
Altera_Forum
Honored Contributor
16 years agoThank you very much. I find the information about reset and exception address. The processor's reset vector is located in ext_flash with offset 0x0 and exception vector is located in sdram with offset 0x20. I think it might be the reason. Thank you again.
BTW, I would like to know whether there is any requirement about these two vectors' location.