Custom Avalon MM-Master component that share On-chip memory with CPU

Hello all,

-- Avalon Master Sample Memory Writer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon_mem_writer is
	port 
	(									
		avm_clk 					: in std_logic;
		avm_reset 				: in std_logic;										
		avm_address				: out std_logic_vector(31 downto 0);		
		avm_write				: out std_logic;
		avm_writedata			: out std_logic_vector(7 downto 0);
		avm_waitrequest		: in std_logic		
	);
end entity;
architecture rtl of avalon_mem_writer is
	type state_type is (idle_state, write_state);	
	signal state : state_type;		
	
	signal avm_address_index : unsigned(31 downto 0);
begin	
	
	process (avm_clk, avm_reset)
   begin				
      if avm_reset = '1' then         
			state 			<= idle_state;			
			avm_address_index	<= x"00000000";
      elsif (rising_edge(avm_clk)) then								
			case state is			
				when idle_state =>						
					if(avm_waitrequest='0') then
						state <= write_state;	
					end if;														
				when write_state =>				
					avm_address_index <= avm_address_index + 1;				
					if(avm_address_index = x"0000000FF") then
						avm_address_index <= x"00000000";		
					end if;
					if(avm_waitrequest='1') then
						state <= idle_state;
					end if;						
			end case;						
		end if;   
	end process;
					
	avm_address 	<= x"00000000"; -- std_logic_vector(avm_address_index);
	avm_writedata 	<= std_logic_vector(avm_address_index(7 downto 0));
		
	process (state)
	begin									
		case state is					
			when idle_state =>
				avm_write 	<= '0';		
			when write_state =>			
				avm_write	<= '1';
			when others => null;			
		end case;
	end process;
	
end rtl;