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Altera_Forum
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11 years ago

Custom Avalon MM-Master component that share On-chip memory with CPU

Hello all, I have a simple custom Avalon MM-Master component -- Avalon Master Sample Memory Writer library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity avalon_mem_wri...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I have some questions for you both. I am working hard to make my custom instruction read from the on_chip_memory_2. My custom instruction is configured as MM Master. It sometimes read correctly, but sometimes don't.

1) Which transfer mode On_chip_memory_2 by default uses? Fixed Latency? Should I wait for waitrequest os for readdatavalid? Looking at On_chip_memory_2 block diagram on Qsys, I realized that it doesn't have either read, waitrequest or readdatavalid signals.

2) If I try your recommendations to use on_chip_memory_2 second port, how should I access it? With an Avalon MM as well or wiring my component direct to its ports?

Thanks,

Gustavo