-- VHDL Custom Instruction Template File for Internal Register Logic
library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_signed.all;

entity CI_multiplier is
	generic (n : integer := 16); 
	port
	(
		signal avalon_clk_in: in std_logic;
		signal avalon_rst_in: in std_logic;
		signal avalon_address: out std_logic_vector(31 downto 0); 
		signal avalon_writedata: out std_logic_vector(31 downto 0);
		signal avalon_readdata: in std_logic_vector(31 downto 0);
		signal avalon_write: out std_logic;   
		signal avalon_read: out std_logic;  
		signal avalon_readdatavalid: in std_logic;
		signal avalon_response: in std_logic_vector(1 downto 0);
		signal avalon_lock: out std_logic;
		signal avalon_waitrequest: in std_logic;
		
		signal ncs_dataa: in std_logic_vector(31 downto 0);   -- Operand A (always required)
		signal ncs_datab: in std_logic_vector(31 downto 0);   -- Operand B (optional)
		signal ncs_clk: in std_logic;                         -- CPU system clock (required for multicycle or extended multicycle)
		signal ncs_reset: in std_logic;                       -- CPU master asynchronous active high reset
		signal ncs_start: in std_logic;                       -- Active high signal used to specify that inputs are valid
		signal ncs_clk_en: in std_logic;                      -- Clock-qualifier (required for multicycle or extended multicycle)
		signal ncs_n: in std_logic_vector(7 downto 0);      -- N-field selector (required for extended);
		signal ncs_result: out std_logic_vector(31 downto 0); -- result (always required)
		signal ncs_done: out std_logic;                       -- Active high signal used to notify the CPU that result is valid
		--signal ncs_a: in std_logic_vector(4 downto 0);      -- Internal operand A index register
		--signal ncs_b: in std_logic_vector(4 downto 0);      -- Internal operand B index register
		signal ncs_c: in std_logic_vector(4 downto 0);        -- Internal result index register
		--signal ncs_readra: in std_logic;                    -- Read operand A from CPU (otherwise use internal operand A)
		--signal ncs_readrb: in std_logic;                    -- Read operand B from CPU (otherwise use internal operand B)
		signal ncs_writerc: in std_logic                      -- Write result to CPU (otherwise write to internal result)
	);		  
end entity CI_multiplier;

architecture behavior of CI_multiplier is
	-- local custom instruction signals
	type read_states_T is (idle, reading);
	signal read_state : read_states_T;
	signal read_data : std_logic_vector (31 downto 0); 
	begin
	
	avalon_address <= ncs_dataa;
	ncs_result <= read_data;
	ncs_done <= '1' when (read_state = reading and avalon_waitrequest = '0')  else '0';
	
	process (avalon_clk_in)
	begin
			if (avalon_rst_in = '1') then
					read_state <= idle;
			elsif rising_edge (avalon_clk_in) then
						case read_state is
									when idle => 
														if (ncs_clk_en = '1' and ncs_start = '1') then
																avalon_read <= '1';
																read_state <= reading;	
														end if;																															
									when reading =>
														if (avalon_waitrequest = '0') then
															read_data <= avalon_readdata;
															avalon_read <= '0';
															read_state <= idle;
														end if;
						end case;
			end if;		
	end process;	
end architecture behavior;