Custom Avalon MM-Master component that share On-chip memory with CPU

Onchip-memory by itself has fixed latency. However, if multiple masters sharing the same onchip-memory port, Qsys interconnect will insert waitrequest/readdatavalid signals.

If you are sharing the same onchip memory port, you will need at least the waitrequest signal. If waitrequest is high, you need to keep the read signal high. Once it de-asserted, the readdata will be valid. This means that you will need to perform multi-cycle type custom instruction that stalls until the waitrequest goes low. I am guessing that the reads sometimes not working for your case because the onchip-memory misses your read access entirely when waitrequest is asserted.

If you enable dual port on the onchip-memory and connect your custom instruction to the second port, it will have fixed latency access. You can just re-use the Avalon MM connections.

Do refer to:https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf, figure 3-3.