Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCustom Avalon MM-Master component that share On-chip memory with CPU
Hello all, I have a simple custom Avalon MM-Master component -- Avalon Master Sample Memory Writer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon_mem_wri...
Altera_ForumHonored Contributor
Honored ContributorI have written testbench and this is result (only difference with code is that address is incremented)
http://www.alteraforum.com/forum/attachment.php?attachmentid=10026&stc=1 When waitrequest is HIGH on the next rising edge "write" signal is LOW, is wrong? I will check Avalon Verification IP Thanks and sorry for my english why? EDIT: With Dual Port onchip-memory works like a charm! But without it does not work..
