Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorCustom Avalon MM-Master component that share On-chip memory with CPU
Hello all, I have a simple custom Avalon MM-Master component -- Avalon Master Sample Memory Writer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity avalon_mem_wri...
Altera_ForumHonored Contributor
Honored ContributorIn the "write_state", when 'waitrequest=1' you transition to "idle_state" where 'write' is de-asserted.
If this happens in your system, the write that you thought you had performed will never have been executed.
