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Altera_Forum
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11 years ago

Custom Avalon MM-Master component that share On-chip memory with CPU

Hello all, I have a simple custom Avalon MM-Master component -- Avalon Master Sample Memory Writer library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity avalon_mem_wri...
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Altera_Forum
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11 years ago

In the example testbench posted I want to write 0 at address 0, 1 at address 1, etc..

"waitrequest" is asserted on falling edge of clock at 0.3ns, at the next rising clock state go to idle and so 2 is not written but when state go again to "write_state" 2 is written correctly at address 2 or I am wrong?