AXI4 DMA Master Error

Hi @Manprocoder,

Could you provide some more details such as Quartus version and board/platform you are building for?

Thanks.

Thank you for the comprehensive overview of the IP in question @Manprocoder

I am trying to find you some help internally as this isn't my area of expertise and nothing is jumping out at me from what you have posted. Hopefully others in the community may also be able to offer some advice.

Seems obvious but I will ask anyway. I am assuming the onchip memory is configured as RAM and not ROM?

Hi experts,

I provide additional details (waveform and C code) to facilitate your supports.

+Quartus Version: Quartus Prime Lite 18.1

+Board: 5CSXFC6D6F31C6 (DE10 Standard)

As I mentioned READ BURST request runs well (handshake arvalid & arready)

Read Waveform:

But WRITE BURST request always encounter problem (no handshake awvalid & awready)

Write Waveform:

C code program:

Thanks for the details @Manprocoder.

From what I can see the platform design looks OK and the NIOS appears to be doing what it should to initialize the DMA so I would conclude the problem is likely to be with the active_ascon IP. I will see if I can get someone from the AXI team to take a look and give some guidance. It will likely require sharing more information about the active_ascon IP block.

Hi @Scot

I provide overall details about active_ascon IP

Allow me to mention my issue again: WRITE BURST is being refused by slave (onchip_memory2_2)

1. Block Diagram

* Function of partial blocks

+ RD_CRF: store config (DMAC config + ASCON config) read from source memory and generate info for WR_REQUEST block

+ STORE_CKN_AD: store those data such as: ascon config, KEY, NONCE, AD, TEXT, TAG (using fifo)

+ FORMAT_DATA: format data read from source memory to run ASCON function (ASCON is algorithm that includes AEAD & HASH)

+ other remaining blocks: function is clearly presented through their name.

2. Data Frame & Timing Diagram

- Data frame (stored in source memory)

- Timing Diagram

3. WR REQUEST BLOCK

- WR_BURST GENERATOR RTL CODE

*Note: I only use information as follows

+ size: 3'b010 (always write 1 word (4 bytes) each transfer)

+ burst: 2'b01 (only use INCR burst)

Hi @ScottW_Altera

I provide additional details on signals of active_ascon IP in platform designer.

- System with Platform Designer Interconnect

Hi Manprocoder,

We checked internally, and we don't have expertise on the active_asconIP, so we aren't able to help. I hope there is community help available. Have you checked with the owner of the IP?

Sue

Hi @SueC_Altera

To be completely upfront, the reasons why I conclude my issue that lies in the interconnect are as follows:
+ The first reason: I rewrite DMAC with Avalon bus, everything is well (read and write occur smoothly)

+ The second one: AXI4 DMAC runs well with READ burst, but the same does not happen to WRITE burst. (My IP issues request, AWVALID is active)

I only assume my problem like this, but I'm not sure 100%.

Best Regards,

Hi Manprocoder,

Are you able to provide your design for us to look at?

Sue

Hi @SueC_Altera

Sure.

My design is in the link below.

https://drive.google.com/drive/folders/1vUU7XVqdJSXgnn0ZmVu3jjvk3DmLEOFW?usp=drive_link