Manprocoder
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Re: AXI4 DMA Master Error
Hi @SueC_Altera To be completely upfront, the reasons why I conclude my issue that lies in the interconnect are as follows: + The first reason: I rewrite DMAC with Avalon bus, everything is well (read and write occur smoothly) + The second one: AXI4 DMAC runs well with READ burst, but the same does not happen to WRITE burst. (My IP issues request, AWVALID is active) I only assume my problem like this, but I'm not sure 100%. Best Regards,Re: AXI4 DMA Master Error
Hi @Scot I provide overall details about active_ascon IP Allow me to mention my issue again: WRITE BURST is being refused by slave (onchip_memory2_2) 1. Block Diagram * Function of partial blocks + RD_CRF: store config (DMAC config + ASCON config) read from source memory and generate info for WR_REQUEST block + STORE_CKN_AD: store those data such as: ascon config, KEY, NONCE, AD, TEXT, TAG (using fifo) + FORMAT_DATA: format data read from source memory to run ASCON function (ASCON is algorithm that includes AEAD & HASH) + other remaining blocks: function is clearly presented through their name. 2. Data Frame & Timing Diagram - Data frame (stored in source memory) - Timing Diagram 3. WR REQUEST BLOCK - WR_BURST GENERATOR RTL CODE *Note: I only use information as follows + size: 3'b010 (always write 1 word (4 bytes) each transfer) + burst: 2'b01 (only use INCR burst)
