Forum Discussion
Manprocoder
New Contributor
New ContributorAXI4 DMA Master Error
Hi expert, I am building SoC system that includes components as follows: + CPU + onchip_memory_2_0 + onchip_memory_2_1 (source address) + onchip_memory_2_2 (destination address) + IP (Active As...
SueC_Altera
Contributor
ContributorHi Manprocoder,
We checked internally, and we don't have expertise on the active_asconIP, so we aren't able to help. I hope there is community help available. Have you checked with the owner of the IP?
Sue
ManprocoderNew Contributor
New ContributorHi @SueC,
I do not think the problem lies in my IP.
I rewrite DMAC with Avalon bus and everything is well during run-time duration.
So, I state that interconnect does not support AXI4 burst (quartus 18.1).
I do not think the problem lies in my IP.
I rewrite DMAC with Avalon bus and everything is well during run-time duration.
So, I state that interconnect does not support AXI4 burst (quartus 18.1).
- SueC_Altera
Hi Manprocoder,
I checked with engineering and they checked the code base for 18.1 interconnect modules and found that AXI4 does support the burst logic as described in the 18.1 UG: https://www.intel.com/content/www/us/en/docs/programmable/683364/18-1/burst-support.html
Please help me understand why you think the problem is in the interconnect?
Thanks,
Sue
