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Manprocoder's avatar
Manprocoder
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1 year ago

AXI4 DMA Master Error

Hi expert, I am building SoC system that includes components as follows: + CPU + onchip_memory_2_0 + onchip_memory_2_1 (source address) + onchip_memory_2_2 (destination address) + IP (Active As...
Nios Cpu
Manprocoder's avatar
Manprocoder
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1 year ago

Hi @SueC_Altera

To be completely upfront, the reasons why I conclude my issue that lies in the interconnect are as follows:
+ The first reason: I rewrite DMAC with Avalon bus, everything is well (read and write occur smoothly)

+ The second one: AXI4 DMAC runs well with READ burst, but the same does not happen to WRITE burst. (My IP issues request, AWVALID is active)

I only assume my problem like this, but I'm not sure 100%.

Best Regards,