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Manprocoder's avatar
Manprocoder
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1 year ago

AXI4 DMA Master Error

Hi expert, I am building SoC system that includes components as follows: + CPU + onchip_memory_2_0 + onchip_memory_2_1 (source address) + onchip_memory_2_2 (destination address) + IP (Active As...
Nios Cpu
ScottW_Altera's avatar
ScottW_Altera
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1 year ago

Thank you for the comprehensive overview of the IP in question @Manprocoder

I am trying to find you some help internally as this isn't my area of expertise and nothing is jumping out at me from what you have posted. Hopefully others in the community may also be able to offer some advice.

Seems obvious but I will ask anyway. I am assuming the onchip memory is configured as RAM and not ROM?

  • Manprocoder's avatar
    Manprocoder
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    1 year ago

    Thanks for your attention @ScottW_Altera

    My problem is too hard for me to address it, and now, I'm totally beat.

    Definitely, I have to rewrite DMAC with AVALON bus.