Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Why does MegaWizard create so many subwire connections even for the simplest ALTPLL?

Why does MegaWizard create so many interdependant subwire connections even for the simplest ALTPLL ( One clock input -> One clock output )?

altpll_component : altpll

PORT MAP (

areset => areset,

inclk => sub_wire4,

locked => sub_wire0,

clk => sub_wire1

);

BEGIN

sub_wire5_bv(0 DOWNTO 0) <= "0";

sub_wire5 <= To_stdlogicvector(sub_wire5_bv);

locked <= sub_wire0;

sub_wire2 <= sub_wire1(0);

c0 <= sub_wire2;

sub_wire3 <= inclk0;

sub_wire4 <= sub_wire5(0 DOWNTO 0) & sub_wire3;

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Because it does. If you're really annoyed with it, I suggest you raise a mysupport request (but Ill doubt you'll get anywhere).

    You could always instantiate the allpll yourself... if you dont mind messing around with the many parameters.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    For FIFO ( made by MegaWizard ) there are no interdependant subwires.

    Maybe there is some hidden meaning in making interdependant subwires especially for ALTPLL?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Ive seen subwires on all sorts of generated code.

    I dont really care, as it usually maps properly, and I only care about the top level.

    You're not supposed to modify generated code (and generated code is always rubbish).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi,

    I'm annoyed by a similar problem, perhaps we mean the same thing...

    Taking your PLL example with 1 clock input and 1 clock output, I always get the conduit signals "areset", "locked" and "phasedone" displayed in my Qsys system as well. And to successfully generate, I have to export these signals, even though they don't really exist :mad:!

    From my point of view, this is not just "rubbish", but a bug. I tried to use the "Remove Dangling Connections" function, but it is always grayed out - no idea when it would be possible to use it.

    https://www.alteraforum.com/forum/attachment.php?attachmentid=7053

    Please let me know if you ment this, or if I'm talking about something differnt.

    Cheers

    Simon
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    Hi,

    Please let me know if you ment this, or if I'm talking about something differnt.

    Cheers

    Simon

    --- Quote End ---

    No, I was talking about different thing ...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Haha you think the subwire thing's bad? All the new MF components creates dozens of systemverilog files. I have a design with 1200 megawizard generated sv files. TBH I'd just like those inferred out

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    ALTPLL is rather simple and I just dont understand the meaning of subwires related to its inclk input.

    Why is it made so sophisticated?

    Or shall I just copy-paste them "as is" into my VHDL code and forget about it?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    you shouldnt be copy and pasting any code generated by the mega wizard. You either instatiate the entity generated or instantiate the PLL yourself.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Hi,

    I'm annoyed by a similar problem, perhaps we mean the same thing...

    Taking your PLL example with 1 clock input and 1 clock output, I always get the conduit signals "areset", "locked" and "phasedone" displayed in my Qsys system as well. And to successfully generate, I have to export these signals, even though they don't really exist :mad:!

    From my point of view, this is not just "rubbish", but a bug. I tried to use the "Remove Dangling Connections" function, but it is always greyed out - no idea when it would be possible to use it.

    Please let me know if you meant this, or if I'm talking about something different.

    Cheers

    Simon

    --- Quote End ---

    And to add insult to injury - if one goes back and removes a clock output that clock output does NOT get removed from the system. Even though it does not exist, you have to export the conduit.

    The collection of defects surrounding the ALTPLL makes me wonder what 'alt' really means.