Forum Discussion
Altera_Forum
Honored Contributor
12 years agoHi,
I'm annoyed by a similar problem, perhaps we mean the same thing... Taking your PLL example with 1 clock input and 1 clock output, I always get the conduit signals "areset", "locked" and "phasedone" displayed in my Qsys system as well. And to successfully generate, I have to export these signals, even though they don't really exist :mad:! From my point of view, this is not just "rubbish", but a bug. I tried to use the "Remove Dangling Connections" function, but it is always grayed out - no idea when it would be possible to use it. https://www.alteraforum.com/forum/attachment.php?attachmentid=7053 Please let me know if you ment this, or if I'm talking about something differnt. Cheers Simon