Agilex 5 SDI 148.5 and 148.35 MHz refclks

I'm working on a design for the Agilex 5 that is going to need to be able to switch between integer and fractional framerates, and I'm trying to figure out and understand the clocking structure involved.

In the GTS SDI II IP User Guide, there is a set of parameters for "Transceiver reference clock frequency" and "Dynamic TX clock switching" under the category "Transceiver Options", however I don't see these parameters in Quartus. Is there somewhere else that I can enable this option to have the two different reference clock frequencies? Do I need this enabled, or is there some other way that I can switch between the two frequencies?

In addition, what does the clocking structure look like to do this? Is there a way to provide 148.5 MHz to the board and then generate the 148.35 from a PLL to be multiplexed? Or do I need to provide both clock frequencies separately? If I need to provide both clock frequencies separately, what pins can I use for the 148.35 MHz reference clock? The two differential pairs of reference clocks for the GTS bank are already being used for the System PLL reference clock and the 148.5 MHz.

Any help with these questions would be greatly appreciated.