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Altera_Forum's avatar
Altera_Forum
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12 years ago

Why does MegaWizard create so many subwire connections even for the simplest ALTPLL?

Why does MegaWizard create so many interdependant subwire connections even for the simplest ALTPLL ( One clock input -> One clock output )? altpll_component : altpll PORT MAP ( ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Haha you think the subwire thing's bad? All the new MF components creates dozens of systemverilog files. I have a design with 1200 megawizard generated sv files. TBH I'd just like those inferred out