Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorWhy does MegaWizard create so many subwire connections even for the simplest ALTPLL?
Why does MegaWizard create so many interdependant subwire connections even for the simplest ALTPLL ( One clock input -> One clock output )? altpll_component : altpll PORT MAP ( ...
Altera_ForumHonored Contributor
Honored ContributorHaha you think the subwire thing's bad? All the new MF components creates dozens of systemverilog files. I have a design with 1200 megawizard generated sv files. TBH I'd just like those inferred out
