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Hi,
I'm annoyed by a similar problem, perhaps we mean the same thing...
Taking your PLL example with 1 clock input and 1 clock output, I always get the conduit signals "areset", "locked" and "phasedone" displayed in my Qsys system as well. And to successfully generate, I have to export these signals, even though they don't really exist :mad:!
From my point of view, this is not just "rubbish", but a bug. I tried to use the "Remove Dangling Connections" function, but it is always greyed out - no idea when it would be possible to use it.
Please let me know if you meant this, or if I'm talking about something different.
Cheers
Simon
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And to add insult to injury - if one goes back and removes a clock output that clock output does NOT get removed from the system. Even though it does not exist, you have to export the conduit.
The collection of defects surrounding the ALTPLL makes me wonder what 'alt' really means.
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