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Altera_Forum
Honored Contributor
Honored ContributorWhy does MegaWizard create so many subwire connections even for the simplest ALTPLL?
Why does MegaWizard create so many interdependant subwire connections even for the simplest ALTPLL ( One clock input -> One clock output )? altpll_component : altpll PORT MAP ( ...
Altera_ForumHonored Contributor
Honored ContributorALTPLL is rather simple and I just dont understand the meaning of subwires related to its inclk input.
Why is it made so sophisticated? Or shall I just copy-paste them "as is" into my VHDL code and forget about it?
