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Длаза's avatar
Длаза
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5 years ago
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Why are signals rx_is_locktodata and rx_is_locktoref always at 0?

Hi, guys!

I created project with 4channel transceiver. But, I can't working because "Transceiver Reset Controller" the controller always holds "rx_ready" at 0.

My project is full compilied. When I look in SignalTap, I see that "rx_is_locktoref='0", "rx_is_locktodata='0". Reference clock for "rx_cdr_refclk" I take from TX:PMA - tx_pma_iqtxrx_clkout.

I posted a project that do not specify all settings. How can I run the CDR unit to set the signals "rx_is_locktoref", "rx_is_locktodata" to 1? Why are they alwyas at 0?

  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,

    As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.

    I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.

    Please let me know if there is any concern. Thank you.

14 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,

    As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.

    I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.

    Please let me know if there is any concern. Thank you.

    • Длаза's avatar
      Длаза
      Icon for New Contributor rankNew Contributor
      5 years ago

      Thanks for the project for Arria10. I loaded to my FPGA and he is worked. I also connected rx_cdr_refclk to pin ATX:refclk, but its not worked.

      Thank you.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Would you mind to elaborate on the "I loaded to my FPGA and he is worked"? Sorry if there is any confusion as you also mention not working after connecting rx_cdr_refclk tp ATX refclk?


    Just to check with you when you create similar design like the one I shared, is it able to run in your C10GX device? For example, can the ATX PLL achieve lock and CDR achieve lock-to-ref if no loopback connection?


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin



    • Длаза's avatar
      Длаза
      Icon for New Contributor rankNew Contributor
      5 years ago

      I took your project as a basis and made an interface between Arria10 and Cyclone10GX. I don't understand what is the difference between the settings of my project and yours. But in your project, both FPGAs have set flags rx_locktoref=1 and rx_locktodata=1 after reseting. Interface between fpga's works.

      In my project i feed rx_crd_refclk to atx_pll_refclk too (156.25MHz).

      Its black magic.

      • CheepinC_altera's avatar
        CheepinC_altera
        Icon for Regular Contributor rankRegular Contributor
        5 years ago

        Hi,

        Thanks for your update. As I understand it, you are interfacing between two devices where you use the RX CDR recovered clock to feed the ATX PLL refclk. For your information, it is recommended to source the RX CDR refclk and ATX PLL refclk both directly from on-board oscillator through dedicated transceiver refclk pins.

        Generally if you are doing re-transmission and required to feed the RX recovered clock to its own TX, you should use clean up PLL to clean up the RX recovered clock before feeding to the TX.

        Please let me know if there is any concern. Thank you.


        Best regards,
        Chee Pin

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Thanks for your update. As I understand it, the ATX PLL has achieved lock. There should be no issue with the ATX PLL and the input refclk. Can you share with me also the other signals ie tx/rx analog resets, tx/rx digital reset, tx/rx_cal_busy to see if can spot any anomaly.


    Regarding the dynamic reconfiguration setting, by default, this setting should not affect the CDR operation. However, probably you could give it a quick try by mimic the same configuration in my design to see if there is any difference.


    Please let me know if there is any concern. Thank you.



    Best regards,

    Chee Pin


    • Длаза's avatar
      Длаза
      Icon for New Contributor rankNew Contributor
      5 years ago

      Because rx_is_locktoref is 0 in my project, then rx_is_locktodata ==0 too and rx_digitalreset == 1 always. Other signals ( *cal_busy, tx_*reset, pll_* ) are set correctly. Waveform mathes with figure 149 and 150 in "Intel Cyclone 10 GX Transceiver PHY User Guide".

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Thanks for your update. Just to check with you if rx_analogreset = 0 in your observation? If rx_analogreset = 0 but rx_is_locktoref stays 0, you might need to double check again on your refclk to CDR. If normal case, after analog reset released, CDR will attempt to achieve lock to the local refclk to CDR and rx_is_locktoref = 1 when lock-to-ref. Then, without valid signal supplied to RX, the CDR rx_is_locktoref and rx_is_locktodata will toggle between 0 and 1 when attempting to achieve lock-to-data mode.


    It is recommend to check on the following as well:


    1. Is the CLKUSR pin connected to free-running oscillator on-board with frequency 100MHz - 125MHz? This is to ensure successful power up calibration of the transceiver to ensure normal functionality.


    2. Is the refclk to CDR connected to free-running oscillator on-board? This clock need to be stable as well before device power up to ensure successful power up calibration.


    By the way, just to check with you on the follwoing:


    1. If you build a design similar to the A10 working design from scratch, with all parameters similar to A10 design, is the design still failing in C10GX device?


    2. Did you manage to get any XCVR design up and running in your C10GX device before?


    3. Are you using any C10GX devkit?


    4. Can you try with this design for C10GX FPGA Devkit from Design Store https://fpgacloud.intel.com/devstore/platform/17.1.1/Pro/cyclone-10-gx-xcvr-toolkit-reference-design/ to see if it work?


    Please let me know if there is any concern. Thank you.


    • Длаза's avatar
      Длаза
      Icon for New Contributor rankNew Contributor
      5 years ago

      Hi!

      I checked my rx_analogreset. It is matched figure 150 of user guide "Intel Arria10 Transceiver PHY..". If there is a problem with refclk, then why is your project working?

      1.CLKUSR is connected to external generator 100MHz. Should i specify somewhere its settings (assignments, device and pin options, constrain)?

      2. refclk is connected to CDR by analogy with your project. Refclk is connected to Si5338, but this generator is programmable. First loaded project configures Si5338, then reconfig fpga, then i loaded my project ( or native1g).

      About Cyclone10GX.

      I have devkit cyclone10GX. There I did my project with Custom Native_PHY (Standart PCS, data rate = 4000Mbps, refclk=625MHz XCVR = 4ch). Its worked. But when transferring from devkit to my hardware with project stops working. I change settings from refclk==625MHz to refclk==156.25MHz.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Thanks for your update. Regarding the C10GX, as I understand it, you have had a test design running on C10GX devkit. However, when you transfer this design to your own C10GX board, the design does not work.


    Based on the observation that C10GX devkit is working fine, this could help to narrow down to your board. Please correct me if I am wrong, in your C10GX board, the ATX PLL has no issue achieving lock. And the TX ready is also High. The issue is only with the RX CDR unable to achieve lock to refclk or data.


    To facilitate the debugging on the C10GX, can you try the following:


    1. Build a simple one channel Native PHY design with data rate 1.25Gbps + 156.25MHz and serial loopback enabled using the latest Q20.3Pro. Leave other settings in Native PHY default.


    2. Test this design on C10GX devkit to see if it works (ATX lock, TX ready, RX CDR LTD). Monitor with SignalTap.


    3. If #2 is working, change the refclk and XCVR pinouts to test with your own C10GX board. No configuration change is required because it is already 156.25MHz.


    4. If #3 is not working, you should further investigate into your board to see if there is any anomaly ie XCVR power supplies, refclk frequencies and etc.


    5. To ensure successful power up calibration, you should ensure the CLKUSR, ATX PLL refclk and CDR refclk are all free-running and stable prior to power up FPGA. These clocks should be directly connected to on-board free-running oscillators.


    6. If the above still not working, you can try again by configuring Native PHY to enable the rx_set_locktodata and rx_set_locktoref ports. This would allow you to manually control the CDR lock mode. Try forcing the CDR to LTR mode to see if it works.


    Please let me know if there is any concern. Thank you.


    Best regards,

    Chee Pin


  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.