Forum Discussion
New ContributorWhy are signals rx_is_locktodata and rx_is_locktoref always at 0?
Hi,
As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.
I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.
Please let me know if there is any concern. Thank you.
Regular ContributorHi,
Thanks for your update. As I understand it, the ATX PLL has achieved lock. There should be no issue with the ATX PLL and the input refclk. Can you share with me also the other signals ie tx/rx analog resets, tx/rx digital reset, tx/rx_cal_busy to see if can spot any anomaly.
Regarding the dynamic reconfiguration setting, by default, this setting should not affect the CDR operation. However, probably you could give it a quick try by mimic the same configuration in my design to see if there is any difference.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorBecause rx_is_locktoref is 0 in my project, then rx_is_locktodata ==0 too and rx_digitalreset == 1 always. Other signals ( *cal_busy, tx_*reset, pll_* ) are set correctly. Waveform mathes with figure 149 and 150 in "Intel Cyclone 10 GX Transceiver PHY User Guide".
