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Длаза's avatar
Длаза
Icon for New Contributor rankNew Contributor
5 years ago
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Why are signals rx_is_locktodata and rx_is_locktoref always at 0?

Hi, guys! I created project with 4channel transceiver. But, I can't working because "Transceiver Reset Controller" the controller always holds "rx_ready" at 0. My project is full compilied. Wh...
  • CheepinC_altera's avatar
    CheepinC_altera
    5 years ago

    Hi,

    As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.

    I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.

    Please let me know if there is any concern. Thank you.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.