Forum Discussion
New ContributorWhy are signals rx_is_locktodata and rx_is_locktoref always at 0?
Hi,
As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.
I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.
Please let me know if there is any concern. Thank you.
Regular ContributorHi,
Would you mind to elaborate on the "I loaded to my FPGA and he is worked"? Sorry if there is any confusion as you also mention not working after connecting rx_cdr_refclk tp ATX refclk?
Just to check with you when you create similar design like the one I shared, is it able to run in your C10GX device? For example, can the ATX PLL achieve lock and CDR achieve lock-to-ref if no loopback connection?
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorI took your project as a basis and made an interface between Arria10 and Cyclone10GX. I don't understand what is the difference between the settings of my project and yours. But in your project, both FPGAs have set flags rx_locktoref=1 and rx_locktodata=1 after reseting. Interface between fpga's works.
In my project i feed rx_crd_refclk to atx_pll_refclk too (156.25MHz).
Its black magic.
- CheepinC_altera
Hi,
Thanks for your update. As I understand it, you are interfacing between two devices where you use the RX CDR recovered clock to feed the ATX PLL refclk. For your information, it is recommended to source the RX CDR refclk and ATX PLL refclk both directly from on-board oscillator through dedicated transceiver refclk pins.
Generally if you are doing re-transmission and required to feed the RX recovered clock to its own TX, you should use clean up PLL to clean up the RX recovered clock before feeding to the TX.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin- Длаза
Hi, Chee!
I didn't want to use RX CDR recovered clock for to feed ATX PLL. I took reference clock from board gen and fed ATX PLL and rx_cdr_refclk. Ref_clk = 156.25MHz. But its didn't work.
Tell me, please, what the scripts "a10_dprio", "a10_xcvr_find_slave" "a10_xcvr_init" "a10_xcvr_procedure" doing?
- CheepinC_altera
Hi,
Thanks for your clarification. By the way, I believe you have checked this but just would like to double confirm, just to check with if you have had a chance to check on the following:
1. Use oscilloscope to measure the on-board ref clock to check if it is of your required frequency ie 156.25MHz?
2. Cross check on the CDR refclk frequency and ATX PLL refclk in IP Editor. Just to ensure they are matching with the value measured in #1.
3. The first step would be to get the ATX PLL up and running. Just would like to check with you if the ATX PLL achieved locked?
Regarding the scripts in the previous shared example design, you may ignored them. The example design was ported from some other toolkit design which are not for this design. Sorry for the confusion.
Please let me know if there is any concern. Thank you.
