Forum Discussion
New ContributorWhy are signals rx_is_locktodata and rx_is_locktoref always at 0?
Hi,
As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.
I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.
Please let me know if there is any concern. Thank you.
Regular ContributorHi,
As I understand it, you observe some issue with the C10GX XCVR where the CDR does not achieve lock-to-data mode. For your information, the CDR refclk and the TX PLL need to be sourced directly from free-running oscillators on-board through dedicated XCVR reference clock pins.
I have attached a simple A10 Native PHY design previous from wiki for your reference. You can refer to the basic block and connection required to see if it is helpful.
Please let me know if there is any concern. Thank you.
New ContributorThanks for the project for Arria10. I loaded to my FPGA and he is worked. I also connected rx_cdr_refclk to pin ATX:refclk, but its not worked.
Thank you.
